Inter-FPGA interconnect topologies exploration for multi-FPGA systems

FPGA Interconnect Topologies Exploration

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance and power of the Tree-bas...

Mesh Routing Topologies for Multi-FPGA Systems

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection sch...

Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures

Most reconngurable multi-fpga architectures have a pro-grammable interconnection network that can be reconngured to implement diierent interconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect connguration stream that correctly implement the partitioned design. We call this pr...

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Article / Book Information 論題(和文) Title(English) Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems 著者(和文) 稲木 雅人, 高島 康裕, 中村 祐一, 高橋 篤司 Authors(English) Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi 出典(和文) , Vol. E91-A, No. 12, pp. 3539-3547 Citation(English) IEICE Trans. Fundamentals, Vol. E91-A, No. 12, pp. 3539-3547 発行日 / ...

Multi - FPGA Systems